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| SI9241AEY New Product Vishay Siliconix Si9241A Single-Ended Bus Transceiver FEATURES * Operating Power Supply Range 6 V VBAT 36 V * Reverse Battery Protection Down to VBAT -24 V * Standby Mode With Very Low Current Consumption IBAT(SB) = 1 A @ VDD = 0.5 V * Low Quiescent Current in OFF Condition IBAT = 120 A and IDD 10 A * ISO 9141 Compatible * * * * * * * Overtemperature Shutdown Function For K Output Defined K Output OFF for Open VBAT or GND Defined Receive Output Status for Open K Input Defined K Output OFF for TX Input Open Open Drain Fault Output 2-kV ESD Typical Transmit Speeds of 200 kBaud DESCRIPTION The SI9241AEY is a monolithic bus transceiver designed to provide bidirectional serial communication in automotive diagnostic applications. The device incorporates protection against overvoltages and short circuits to VBAT. The transceiver pin is protected and can be driven beyond the VBAT voltage. The SI9241AEY is built on the Siliconix BiC/DMOS process. An epitaxial layer prevents latchup. The RX output is capable of driving CMOS or 1 LSTTL load. The SI9241AEY is available in a space efficient 8-pin SO package. It operates reliably over the automotive temperature range (-40 to 125C). PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM FaxBack 408-970-5600, request 70787 www.siliconix.com S-60752--Rev. C, 05-Apr-99 1 SI9241AEY Vishay Siliconix New Product OUTPUT TABLE AND STATE DIAGRAMS Inputs CS 0 0 X 0 State Variable A 1 1 0 1 Output Table RX 0 1 K K TX 0 1 X X B 1 1 1 0 K 0 1 HiZ HiZ FAULT 1 1 0 0 Comments Over Temp Short Circuit 1 1 X X 1 1 1 1 0 1 0 1 1 1 Receive Mode Note: Over Temp is an internal condition, not meant to be a logic signal. X = "1" or "0" HiZ = High Impedance State ABSOLUTE MAXIMUM RATINGS Voltage Referenced to Ground Voltage On VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V Voltage K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -16 V to (VBAT + 1 V) Voltage Difference V(VBAT, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 V Voltage or Max. Current On Any Pin (Except VBAT , K) . . . . . . . . . . . . . . . . -0.3 V to (VDD + 0.3 V) or 10 mA Voltage on VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V K Pin Only, Short Circuit Duration (to VBAT or GND) . . . . . Continuous Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . -40 to 125C Junction and Storage Temperature . . . . . . . . . . . . . . . . . -55 to 150C Thermal Resistance JA . . . . . . . . . . . . . . . . . . . . . . . . . . . .125C/W Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Voltage Referenced to Ground VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5 V to 5.5 V VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V to 36 V K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 36 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter Symbol VDD = 4.5 to 5.5 V VBAT = 6 to 36 V Limits E Suffix: -40 to 125C Temp a Minb Typc Maxb Unit Transmitter And Logic Levels CS, TX Input Low Voltage CS, TX Input High Voltage TX Input Capacitanced CS, TX Input Pull-up Resistance VILT VIHT CINT RTX, RCS VDD = 5.5 V, TX or CS = 1.5 V, 3.5 V Full Full Full Full 10 20 3.5 10 40 1.5 V pF k K Transmit RL = 510 5% , VBAT = 6 to 18 V K Output Low Voltage VOLK RL = 1 k 5% , VBAT = 16 to 36 V RL = 510 5% , VBAT = 4.5 V K Output High Voltage K Rise, Fall Times VOHK tr, tf RL = 510 5% , VBAT = 4.5 to 18 V RL = 1 k 5% , VBAT = 16 to 36 V See Test Circuit Full Full Full Full Full Full 0.95 VBAT 0.95 VBAT 9.6 s 0.2 VBAT 0.2 VBAT 1.2 V S-60752--Rev. C, 05-Apr-99 2 FaxBack 408-970-5600, request 70787 www.siliconix.com SI9241AEY New Product SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter K Output Sink Resistance K Output Capacitance d Vishay Siliconix Limits E Suffix: -40 to 125C Symbol Rsi CO VDD = 4.5 to 5.5 V VBAT = 6 to 36 V CS = 0 V, TX = 0 V Temp a Minb Typc Maxb 110 20 Unit pF Full Full Receiver K Input Low Voltage K Input High Voltage K Input Hysteresisc, d VILK VIHK VHYS IIHK VOLR RRX RL = 510 k 5% , VBAT = 6 to 18 V CL = 10 nF, See Test Circuit RL = 1 k 5% , VBAT = 16 to 36 V CL = 4.7 nF, See Test Circuit RL = 510 k 5% , VBAT = 6 to 18 V CL = 10 nF, See Test Circuit RL = 1 k 5% , VBAT = 16 to 36 V CL = 4.7 nF, See Test Circuit CS = TX = 0 V, VBAT 16 V CS = High, VBAT 12 V, TX = High VDD 0.5 V, VBAT 12 V VDD 5.5 V, TX = 0 V CS = High, VBAT 12 V, TX = Highf RL = 510 , CL = 10 nF 6 V < VBAT < 16 V, CRX = 20 pF 6 V < VBAT < 16 V, RK = 510 CK 1.3 nF CS = TX = 0 V, K = VBAT, IOLF = 1 mA Temperature Rising f Full Full Full VILK = VBAT CS = 4 V VILK = 0.35 VBAT IOLR = 1 mA Full Full Full Full Full Full Full 5 3 3 3 3 0.65 VBAT 0.05 VBAT 0.35 VBAT V K Input Currents RX Output Low Voltage RX Pull-up Resistance 20 0.4 20 10 10 A V k RX Turn On Delay td(on) s 10 10 RX Turn Off Delay td(off) Supplies Bat Supply Current On Bat Supply Current Off Bat Supply Current Standby Logic Supply Current On Logic Supply Current Off IBAT(on) IBAT(off) IBAT(SB) IDD(on) IDD(off) Full Full Full Full Full 1.2 120 <1 1.4 3 220 10 2.3 10 mA A mA A Miscellaneous TX Transmit Baud Rate RX Receive Baud Ratec Transmission Frequency Fault Output Low Voltage CS Minimum Pulse Width d, e BRT BRR fK-RXK VOLF tcs TSHUT THYST Full Full Full Full Full 10.4 200 50 200 0.4 1 160 180 30 kBau d kHz V s C Over Temperature Shutdownd Temperature Shutdown Hysteresisc Notes a. Room = 25C, Cold and Hot = as determined by the operating temperature suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Guaranteed by design, not subject to production test. e. Minimum pulse width to reset a fault condition. f. High referes to Logic High and Low refers to Logic Low. FaxBack 408-970-5600, request 70787 www.siliconix.com S-60752--Rev. C, 05-Apr-99 3 SI9241AEY Vishay Siliconix PIN CONFIGURATION ORDERING INFORMATION Part Number SI9241AEY New Product Temperature Range -40 to 125C PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 Symbol VDD TX CS FAULT GND K VBAT RX Positive Power Supply Transmit, Input Chip Select, Input Fault, Open Drain Output Ground Connection Transmit/Receive, Bidirectional Battery Power Supply Receiver, Output Description FUNCTIONAL DESCRIPTION The SI9241AEY can be either in transmit or receive mode and it contains over temperature, short circuit and open VBAT fault detection circuits. The voltage on K is internally compared to VBAT/2. If the voltage on the K pin is less than V BAT/2 then RX output will be "low." If the voltage on the K pin is greater than VBAT/2 then RX output will be "high." In order to be in transmit mode, CS must be set "low." When CS and TX are set "low" the internal MOSFET will turn on, causing the K pin to be "low." In the transmit mode, the processor monitors RX and TX. When the two mirror each other there is no fault. In the event of over temperature, short circuit to VBAT or open VBAT, the SI9241AEY will turn off the K output to protect the IC and the external open drain FAULT pin will be asserted. The K pin will stay in high impedance and RX will follow the K pin. The fault will be reset when CS is toggled high. RX, CS and TX pins have an internal pull up resistor to VDD while the K pin has internal pull down resistors. When any one of the TX, VBAT or GND pins is open the K output is off. When CS is set "high" the SI9241AEY is in receive mode and the internal MOSFET for the K pin is turned off. The RX output will follow the K pin. If CS is "low" while the IC is receiving data, an incorrect fault signal will occur. To inhibit the short detect, tie CS and TX together. S-60752--Rev. C, 05-Apr-99 4 FaxBack 408-970-5600, request 70787 www.siliconix.com SI9241AEY New Product TEST CIRCUIT AND TIMING DIAGRAMS (TRANSMIT ONLY) Vishay Siliconix APPLICATION CIRCUIT FaxBack 408-970-5600, request 70787 www.siliconix.com S-60752--Rev. C, 05-Apr-99 5 |
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